Code:
//
// ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
// º This file is generated by The Interactive Disassembler (IDA) º
// º Copyright (c) 2005 by DataRescue sa/nv, <[email protected]> º
// º Licensed to: Charlie Wallace - finiteMonkeys (1-user Advanced 04/2005) º
// ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ
//
//
// This file contains the user-defined type definitions.
// To use it press F2 in IDA and enter the name of this file.
//
#define UNLOADED_FILE 1
#include <idc.idc>
static main(void) {
Structures(); // structure types
Bytes_0();
// Enums(); // enumerations
LowVoids(0x0);
HighVoids(0x80000);
}
static Enums_0(id) {
id = AddEnum(-1,"toucan",0x100000);
AddConstEx(id,"SIMCR", 0XFFFA00,-1);
AddConstEx(id,"TPUMCR" ,0XFFFE00,-1);// tpu module control register
AddConstEx(id,"TPUCFG" ,0XFFFE02,-1);// configuration register
AddConstEx(id,"DSCR" ,0XFFFE04,-1);// development support control register
AddConstEx(id,"DSSR" ,0XFFFE06,-1);// development support status register
AddConstEx(id,"TPUICR" ,0XFFFE08,-1);// interrupt configuration register
AddConstEx(id,"TPUIER" ,0XFFFE0A,-1);// interrupt enable register
AddConstEx(id,"CFSR0" ,0XFFFE0C,-1);// channel function select register 0
AddConstEx(id,"CFSR1" ,0XFFFE0E,-1);// channel function select register 1
AddConstEx(id,"CFSR2" ,0XFFFE10,-1);// channel function select register 2
AddConstEx(id,"CFSR3" ,0XFFFE12,-1);// channel function select register 3
AddConstEx(id,"HSR0" ,0XFFFE14,-1);// host sequence register 0
AddConstEx(id,"HSR1" ,0XFFFE16,-1);// host sequence register 1
AddConstEx(id,"HSRR0" ,0XFFFE18,-1);// host service request register 0
AddConstEx(id,"HSRR1" ,0XFFFE1A,-1);// host service request register 1
AddConstEx(id,"CPR0" ,0XFFFE1C,-1);// channel priority register 0
AddConstEx(id,"CPR1" ,0XFFFE1E,-1);// channel priority register 1
AddConstEx(id,"TPUISR" ,0XFFFE20,-1);// interrupt status register
AddConstEx(id,"LINK" ,0XFFFE22,-1);//
AddConstEx(id,"SGLR" ,0XFFFE24,-1);// service grant latch register
AddConstEx(id,"DCNR" ,0XFFFE26,-1);// decoded channel number register
AddConstEx(id,"TPUPRAM",0XFFFF00,-1);// start of tpu parameter RAM
AddConstEx(id,"SIMMCR" ,0XFFFA00,-1);// sim module configuratio register
AddConstEx(id,"SIMTR" ,0XFFFA02,-1);// sim test register
AddConstEx(id,"SYNCR" ,0XFFFA04,-1);// clock synthesizer control
AddConstEx(id,"RSR" ,0XFFFA07,-1);// reset status register
AddConstEx(id,"SIMTRE" ,0XFFFA08,-1);// sim module test e
AddConstEx(id,"PORTE" ,0XFFFA11,-1);// port e data register
AddConstEx(id,"DDRE" ,0XFFFA15,-1);// port e data direction register
AddConstEx(id,"PEPAR" ,0XFFFA17,-1);// port e pin assignment register
AddConstEx(id,"PORTF" ,0XFFFA19,-1);// port f data register
AddConstEx(id,"DDRF" ,0XFFFA1D,-1);// port f data direction register
AddConstEx(id,"PFPAR" ,0XFFFA1F,-1);// port f pin assignment register
AddConstEx(id,"SYPCR" ,0XFFFA21,-1);// system protection control
AddConstEx(id,"PICR" ,0XFFFA22,-1);// periodic interrupt control
AddConstEx(id,"PITR" ,0XFFFA24,-1);// periodic interrupt timer
AddConstEx(id,"SWSR" ,0XFFFA27,-1);// watchdog software service register
AddConstEx(id,"TSTMSRA",0XFFFA30,-1);// test master shift register a
AddConstEx(id,"TSTMSRB",0XFFFA32,-1);// test master shift register b
AddConstEx(id,"TSTSC" ,0XFFFA34,-1);// test shift count register
AddConstEx(id,"TSTRC" ,0XFFFA36,-1);// test repetition count register
AddConstEx(id,"CREG" ,0XFFFA38,-1);// test module control
AddConstEx(id,"DREG" ,0XFFFA3A,-1);// test distributed control
AddConstEx(id,"PORTC" ,0XFFFA41,-1);// port c data register
AddConstEx(id,"CSPAR0" ,0XFFFA44,-1);// chip select pin assignment register 0
AddConstEx(id,"CSPAR1" ,0XFFFA46,-1);// chip select pin assignment register 1
AddConstEx(id,"CSBARBT",0XFFFA48,-1);// CSBOOT base address register
AddConstEx(id,"CSORBT" ,0XFFFA4A,-1);// CSBOOT option register
AddConstEx(id,"CSBAR0" ,0XFFFA4C,-1);// chip select 0 base address register
AddConstEx(id,"CSOR0" ,0XFFFA4E,-1);// chip select 0 option register
AddConstEx(id,"CSBAR1" ,0XFFFA50,-1);// chip select 0 base address register
AddConstEx(id,"CSOR1" ,0XFFFA52,-1);// chip select 0 option register
AddConstEx(id,"CSBAR2" ,0XFFFA54,-1);// chip select 0 base address register
AddConstEx(id,"CSOR2" ,0XFFFA56,-1);// chip select 0 option register
AddConstEx(id,"CSBAR3" ,0XFFFA58,-1);// chip select 0 base address register
AddConstEx(id,"CSOR3" ,0XFFFA5A,-1);// chip select 0 option register
AddConstEx(id,"CSBAR4" ,0XFFFA5C,-1);// chip select 0 base address register
AddConstEx(id,"CSOR4" ,0XFFFA5E,-1);// chip select 0 option register
AddConstEx(id,"CSBAR5" ,0XFFFA60,-1);// chip select 0 base address register
AddConstEx(id,"CSOR5" ,0XFFFA62,-1);// chip select 0 option register
AddConstEx(id,"CSBAR6" ,0XFFFA64,-1);// chip select 0 base address register
AddConstEx(id,"CSOR6" ,0XFFFA66,-1);// chip select 0 option register
AddConstEx(id,"CSBAR7" ,0XFFFA68,-1);// chip select 0 base address register
AddConstEx(id,"CSOR7" ,0XFFFA6A,-1);// chip select 0 option register
AddConstEx(id,"CSBAR8" ,0XFFFA6C,-1);// chip select 0 base address register
AddConstEx(id,"CSOR8" ,0XFFFA6E,-1);// chip select 0 option register
AddConstEx(id,"CSBAR9" ,0XFFFA70,-1);// chip select 0 base address register
AddConstEx(id,"CSOR9" ,0XFFFA72,-1);// chip select 0 option register
AddConstEx(id,"CSBAR10",0XFFFA74,-1);// chip select 0 base address register
AddConstEx(id,"CSOR10" ,0XFFFA76,-1);// chip select 0 option register
AddConstEx(id,"QMCR" ,0XFFFC00,-1);// use full 32-bit address for sign extended addresses
AddConstEx(id,"QTEST" ,0XFFFC02,-1);// qsm test register
AddConstEx(id,"QILR" ,0XFFFC04,-1);// qsm interrupt level register
AddConstEx(id,"QIVR" ,0XFFFC05,-1);// qsm interrupt vector register
AddConstEx(id,"SCCR0" ,0XFFFC06,-1);// sci control register 0
AddConstEx(id,"SCCR1" ,0XFFFC08,-1);// sci control register 1
AddConstEx(id,"SCSR" ,0XFFFC0A,-1);// sci status register
AddConstEx(id,"SCDR" ,0XFFFC0C,-1);// sci data register
AddConstEx(id,"QPDR" ,0XFFFC15,-1);// qsm port data register
AddConstEx(id,"QPAR" ,0XFFFC16,-1);// qsm pin assignment register
AddConstEx(id,"QDDR" ,0XFFFC17,-1);// qsm data direction register
AddConstEx(id,"SPCR0" ,0XFFFC18,-1);// qspi control register 0
AddConstEx(id,"SPCR1" ,0XFFFC1A,-1);// qspi control register 1
AddConstEx(id,"SPCR2" ,0XFFFC1C,-1);// qspi control register 2
AddConstEx(id,"SPCR3" ,0XFFFC1E,-1);// qspi control register 3
AddConstEx(id,"SPSR" ,0XFFFC20,-1);// qspi status register
AddConstEx(id,"QRXD" ,0XFFFD00,-1);// qspi receive data buffer start
AddConstEx(id,"QTXD" ,0XFFFD20,-1);// qspi transmit data buffer start
AddConstEx(id,"QCMD" ,0XFFFD40,-1);// qspi command buffer start
AddConstEx(id,"RAMMCR" ,0XFFFB00,-1);// ram module configuration register
AddConstEx(id,"RAMTST" ,0XFFFB02,-1);// ram module test register
AddConstEx(id,"RAMBAR" ,0XFFFB04,-1);// ram base address register
AddConstEx(id,"RAMBAH",0XFFFB44 ,-1);
AddConstEx(id,"RAMBAL",0XFFFB46 ,-1);
AddConstEx(id,"TOPRAM",0XFFE800 ,-1);
AddConstEx(id,"CANMCR",0XFFF080 ,-1);
return id;
}
//------------------------------------------------------------------------
// Information about enum types
static Enums(void) {
auto id;
id = Enums_0(id);
}
static Structures_0(id) {
id = AddStrucEx(-1,"fuelrow",0);
id = AddStrucEx(-1,"struc_3",0);
id = AddStrucEx(-1,"fuel_map",0);
id = GetStrucIdByName("fuelrow");
AddStrucMember(id,"field_0", 0X0, 0x10000400,-1, 2);
AddStrucMember(id,"field_2", 0X2, 0x10000400,-1, 2);
AddStrucMember(id,"field_4", 0X4, 0x10000400,-1, 2);
AddStrucMember(id,"field_6", 0X6, 0x10000400,-1, 2);
AddStrucMember(id,"field_8", 0X8, 0x10000400,-1, 2);
AddStrucMember(id,"field_A", 0XA, 0x10000400,-1, 2);
AddStrucMember(id,"field_C", 0XC, 0x10000400,-1, 2);
AddStrucMember(id,"field_E", 0XE, 0x10000400,-1, 2);
AddStrucMember(id,"field_10", 0X10, 0x10000400,-1, 2);
AddStrucMember(id,"field_12", 0X12, 0x10000400,-1, 2);
AddStrucMember(id,"field_14", 0X14, 0x10000400,-1, 2);
AddStrucMember(id,"field_16", 0X16, 0x10000400,-1, 2);
AddStrucMember(id,"field_18", 0X18, 0x10000400,-1, 2);
AddStrucMember(id,"field_1A", 0X1A, 0x10000400,-1, 2);
AddStrucMember(id,"field_1C", 0X1C, 0x10000400,-1, 2);
AddStrucMember(id,"field_1E", 0X1E, 0x10000400,-1, 2);
id = GetStrucIdByName("struc_3");
id = GetStrucIdByName("fuel_map");
return id;
}
//------------------------------------------------------------------------
// Information about structure types
static Structures(void) {
auto id;
id = Structures_0(id);
}
//------------------------------------------------------------------------
// Information about bytes
static Bytes_0(void) {
auto x;
#define id x
MakeName (0XFFE800, "stack");
MakeName(0XFFFE00 ,"tpumcr");// tpu module control register
MakeName(0XFFFE02 ,"tpucfg");// configuration register
MakeName(0XFFFE04 ,"dscr");// development support control register
MakeName(0XFFFE06 ,"dssr");// development support status register
MakeName(0XFFFE08 ,"tpuicr");// interrupt configuration register
MakeName(0XFFFE0A ,"tpuier");// interrupt enable register
MakeName(0XFFFE0C ,"cfsr0");// channel function select register 0
MakeName(0XFFFE0E ,"cfsr1");// channel function select register 1
MakeName(0XFFFE10 ,"cfsr2");// channel function select register 2
MakeName(0XFFFE12 ,"cfsr3");// channel function select register 3
MakeName(0XFFFE14 ,"hsr0");// host sequence register 0
MakeName(0XFFFE16 ,"hsr1");// host sequence register 1
MakeName(0XFFFE18 ,"hsrr0");// host service request register 0
MakeName(0XFFFE1A ,"hsrr1");// host service request register 1
MakeName(0XFFFE1C ,"cpr0");// channel priority register 0
MakeName(0XFFFE1E ,"cpr1");// channel priority register 1
MakeName(0XFFFE20 ,"tpuisr");// interrupt status register
MakeName(0XFFFE22 ,"link");//
MakeName(0XFFFE24 ,"sglr");// service grant latch register
MakeName(0XFFFE26 ,"dcnr");// decoded channel number register
MakeName(0XFFFF00 ,"tpupram");// start of tpu parameter RAM
MakeName(0XFFFA00 ,"simmcr");// sim module configuratio register
MakeName(0XFFFA02 ,"simtr");// sim test register
MakeName(0XFFFA04 ,"syncr");// clock synthesizer control
MakeName(0XFFFA07 ,"rsr");// reset status register
MakeName(0XFFFA08 ,"simtre");// sim module test e
MakeName(0XFFFA11 ,"porte");// port e data register
MakeName(0XFFFA15 ,"ddre");// port e data direction register
MakeName(0XFFFA17 ,"pepar");// port e pin assignment register
MakeName(0XFFFA19 ,"portf");// port f data register
MakeName(0XFFFA1D ,"ddrf");// port f data direction register
MakeName(0XFFFA1F ,"pfpar");// port f pin assignment register
MakeName(0XFFFA21 ,"sypcr");// system protection control
MakeName(0XFFFA22 ,"picr");// periodic interrupt control
MakeName(0XFFFA24 ,"pitr");// periodic interrupt timer
MakeName(0XFFFA27 ,"swsr");// watchdog software service register
MakeName(0XFFFA30 ,"tstmsra");// test master shift register a
MakeName(0XFFFA32 ,"tstmsrb");// test master shift register b
MakeName(0XFFFA34 ,"tstsc");// test shift count register
MakeName(0XFFFA36 ,"tstrc");// test repetition count register
MakeName(0XFFFA38 ,"creg");// test module control
MakeName(0XFFFA3A ,"dreg");// test distributed control
MakeName(0XFFFA41 ,"portc");// port c data register
MakeName(0XFFFA44 ,"cspar0");// chip select pin assignment register 0
MakeName(0XFFFA46 ,"cspar1");// chip select pin assignment register 1
MakeName(0XFFFA48 ,"csbarbt");// CSBOOT base address register
MakeName(0XFFFA4A ,"csorbt");// CSBOOT option register
MakeName(0XFFFA4C ,"csbar0");// chip select 0 base address register
MakeName(0XFFFA4E ,"csor0");// chip select 0 option register
MakeName(0XFFFA50 ,"csbar1");// chip select 0 base address register
MakeName(0XFFFA52 ,"csor1");// chip select 0 option register
MakeName(0XFFFA54 ,"csbar2");// chip select 0 base address register
MakeName(0XFFFA56 ,"csor2");// chip select 0 option register
MakeName(0XFFFA58 ,"csbar3");// chip select 0 base address register
MakeName(0XFFFA5A ,"csor3");// chip select 0 option register
MakeName(0XFFFA5C ,"csbar4");// chip select 0 base address register
MakeName(0XFFFA5E ,"csor4");// chip select 0 option register
MakeName(0XFFFA60 ,"csbar5");// chip select 0 base address register
MakeName(0XFFFA62 ,"csor5");// chip select 0 option register
MakeName(0XFFFA64 ,"csbar6");// chip select 0 base address register
MakeName(0XFFFA66 ,"csor6");// chip select 0 option register
MakeName(0XFFFA68 ,"csbar7");// chip select 0 base address register
MakeName(0XFFFA6A ,"csor7");// chip select 0 option register
MakeName(0XFFFA6C ,"csbar8");// chip select 0 base address register
MakeName(0XFFFA6E ,"csor8");// chip select 0 option register
MakeName(0XFFFA70 ,"csbar9");// chip select 0 base address register
MakeName(0XFFFA72 ,"csor9");// chip select 0 option register
MakeName(0XFFFA74 ,"csbar10");// chip select 0 base address register
MakeName(0XFFFA76 ,"csor10");// chip select 0 option register
MakeName(0XFFFC00 ,"qmcr");// use full 32-bit address for sign extended addresses
MakeName(0XFFFC02 ,"qtest");// qsm test register
MakeName(0XFFFC04 ,"qilr");// qsm interrupt level register
MakeName(0XFFFC05 ,"qivr");// qsm interrupt vector register
MakeName(0XFFFC06 ,"sccr0");// sci control register 0
MakeName(0XFFFC08 ,"sccr1");// sci control register 1
MakeName(0XFFFC0A ,"scsr");// sci status register
MakeName(0XFFFC0C ,"scdr");// sci data register
MakeName(0XFFFC15 ,"qpdr");// qsm port data register
MakeName(0XFFFC16 ,"qpar");// qsm pin assignment register
MakeName(0XFFFC17 ,"qddr");// qsm data direction register
MakeName(0XFFFC18 ,"spcr0");// qspi control register 0
MakeName(0XFFFC1A ,"spcr1");// qspi control register 1
MakeName(0XFFFC1C ,"spcr2");// qspi control register 2
MakeName(0XFFFC1E ,"spcr3");// qspi control register 3
MakeName(0XFFFC20 ,"spsr");// qspi status register
MakeName(0XFFFD00 ,"qrxd");// qspi receive data buffer start
MakeName(0XFFFD20 ,"qtxd");// qspi transmit data buffer start
MakeName(0XFFFD40 ,"qcmd");// qspi command buffer start
MakeName(0XFFFB00 ,"rammcr");// ram module configuration register
MakeName(0XFFFB02 ,"ramtst");// ram module test register
MakeName(0XFFFB04 ,"rambar");// ram base address register
MakeName(0XFFFB44 ,"RAMBAH");
MakeName(0XFFFB46 ,"RAMBAL");
MakeName(0XFFE800 ,"TOPRAM");
MakeName(0XFFF080 ,"CANMCR");
MakeRptCmt(0XFFE800, "stack ptr");
MakeRptCmt(0XFFFE00, "tpu module control register");
MakeRptCmt(0XFFFE02, "configuration register");
MakeRptCmt(0XFFFE04, "development support control register");
MakeRptCmt(0XFFFE06, "development support status register");
MakeRptCmt(0XFFFE08, "interrupt configuration register");
MakeRptCmt(0XFFFE0A, "interrupt enable register");
MakeRptCmt(0XFFFE0C, "channel function select register 0");
MakeRptCmt(0XFFFE0E, "channel function select register 1");
MakeRptCmt(0XFFFE10, "channel function select register 2");
MakeRptCmt(0XFFFE12, "channel function select register 3");
MakeRptCmt(0XFFFE14, "host sequence register 0");
MakeRptCmt(0XFFFE16, "host sequence register 1");
MakeRptCmt(0XFFFE18, "host service request register 0");
MakeRptCmt(0XFFFE1A, "host service request register 1");
MakeRptCmt(0XFFFE1C, "channel priority register 0");
MakeRptCmt(0XFFFE1E, "channel priority register 1");
MakeRptCmt(0XFFFE20, "interrupt status register");
MakeRptCmt(0XFFFE22, "link ");
MakeRptCmt(0XFFFE24, "service grant latch register");
MakeRptCmt(0XFFFE26, "decoded channel number register");
MakeRptCmt(0XFFFF00, "start of tpu parameter RAM");
MakeRptCmt(0XFFFA00, "sim module configuratio register");
MakeRptCmt(0XFFFA02, "sim test register");
MakeRptCmt(0XFFFA04, "clock synthesizer control");
MakeRptCmt(0XFFFA07, "reset status register");
MakeRptCmt(0XFFFA08, "sim module test e");
MakeRptCmt(0XFFFA11, "port e data register");
MakeRptCmt(0XFFFA15, "port e data direction register");
MakeRptCmt(0XFFFA17, "port e pin assignment register");
MakeRptCmt(0XFFFA19, "port f data register");
MakeRptCmt(0XFFFA1D, "port f data direction register");
MakeRptCmt(0XFFFA1F, "port f pin assignment register");
MakeRptCmt(0XFFFA21, "system protection control");
MakeRptCmt(0XFFFA22, "periodic interrupt control");
MakeRptCmt(0XFFFA24, "periodic interrupt timer");
MakeRptCmt(0XFFFA27, "watchdog software service register");
MakeRptCmt(0XFFFA30, "test master shift register a");
MakeRptCmt(0XFFFA32, "test master shift register b");
MakeRptCmt(0XFFFA34, "test shift count register");
MakeRptCmt(0XFFFA36, "test repetition count register");
MakeRptCmt(0XFFFA38, "test module control");
MakeRptCmt(0XFFFA3A, "test distributed control");
MakeRptCmt(0XFFFA41, "port c data register");
MakeRptCmt(0XFFFA44, "chip select pin assignment register 0");
MakeRptCmt(0XFFFA46, "chip select pin assignment register 1");
MakeRptCmt(0XFFFA48, "CSBOOT base address register");
MakeRptCmt(0XFFFA4A, "CSBOOT option register");
MakeRptCmt(0XFFFA4C, "chip select 0 base address register");
MakeRptCmt(0XFFFA4E, "chip select 0 option register");
MakeRptCmt(0XFFFA50, "chip select 0 base address register");
MakeRptCmt(0XFFFA52, "chip select 0 option register");
MakeRptCmt(0XFFFA54, "chip select 0 base address register");
MakeRptCmt(0XFFFA56, "chip select 0 option register");
MakeRptCmt(0XFFFA58, "chip select 0 base address register");
MakeRptCmt(0XFFFA5A, "chip select 0 option register");
MakeRptCmt(0XFFFA5C, "chip select 0 base address register");
MakeRptCmt(0XFFFA5E, "chip select 0 option register");
MakeRptCmt(0XFFFA60, "chip select 0 base address register");
MakeRptCmt(0XFFFA62, "chip select 0 option register");
MakeRptCmt(0XFFFA64, "chip select 0 base address register");
MakeRptCmt(0XFFFA66, "chip select 0 option register");
MakeRptCmt(0XFFFA68, "chip select 0 base address register");
MakeRptCmt(0XFFFA6A, "chip select 0 option register");
MakeRptCmt(0XFFFA6C, "chip select 0 base address register");
MakeRptCmt(0XFFFA6E, "chip select 0 option register");
MakeRptCmt(0XFFFA70, "chip select 0 base address register");
MakeRptCmt(0XFFFA72, "chip select 0 option register");
MakeRptCmt(0XFFFA74, "chip select 0 base address register");
MakeRptCmt(0XFFFA76, "chip select 0 option register");
MakeRptCmt(0XFFFC00, "use full 32-bit address for sign extended addresses");
MakeRptCmt(0XFFFC02, "qsm test register");
MakeRptCmt(0XFFFC04, "qsm interrupt level register");
MakeRptCmt(0XFFFC05, "qsm interrupt vector register");
MakeRptCmt(0XFFFC06, "sci control register 0");
MakeRptCmt(0XFFFC08, "sci control register 1");
MakeRptCmt(0XFFFC0A, "sci status register");
MakeRptCmt(0XFFFC0C, "sci data register");
MakeRptCmt(0XFFFC15, "qsm port data register");
MakeRptCmt(0XFFFC16, "qsm pin assignment register");
MakeRptCmt(0XFFFC17, "qsm data direction register");
MakeRptCmt(0XFFFC18, "qspi control register 0");
MakeRptCmt(0XFFFC1A, "qspi control register 1");
MakeRptCmt(0XFFFC1C, "qspi control register 2");
MakeRptCmt(0XFFFC1E, "qspi control register 3");
MakeRptCmt(0XFFFC20, "qspi status register");
MakeRptCmt(0XFFFD00, "qspi receive data buffer start");
MakeRptCmt(0XFFFD20, "qspi transmit data buffer start");
MakeRptCmt(0XFFFD40, "qspi command buffer start");
MakeRptCmt(0XFFFB00, "ram module configuration register");
MakeRptCmt(0XFFFB02, "ram module test register");
MakeRptCmt(0XFFFB04, "ram base address register");
MakeRptCmt(0XFFFB44, "ram base address register high");
MakeRptCmt(0XFFFB46, "ram base address register low");
MakeRptCmt(0XFFF080, "");
}
// End of file.
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